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FEATURES Low Power Consumption: Precision Voltage Monitor 2% Tolerance on ADM800L/M Reset Time Delay--200 ms, or Adjustable 1 A Standby Current Automatic Battery Backup Power Switching Fast Onboard Gating of Chip Enable Signals Also Available in TSSOP Package (ADM691A) APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems Critical P Power Monitoring
Microprocessor Supervisory Circuits ADM691A/ADM693A/ADM800L/M
FUNCTIONAL BLOCK DIAGRAM
BATT ON 4.65V1 VCC VOUT VBATT CHIP ENABLE OUTPUT CONTROL CEIN CEOUT LOW LINE
OSC IN OSC SEL
RESET & WATCHDOG TIMEBASE
RESET & GENERATOR
RESET RESET
WATCHDOG INPUT (WDI)
WATCHDOG TRANSITION DETECTOR
WATCHDOG TIMER
WATCHDOG OUTPUT (WDO) POWER FAIL OUTPUT (PFO)
GENERAL DESCRIPTION
POWER FAIL INPUT (PFI) 1.25V
The ADM691A/ADM693A/ADM800L/ADM800M family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include P reset, backup-battery switchover, watchdog timer, CMOS RAM write protection, and power-failure warning. The family of products provides an upgrade for the MAX691A/93A/800M family of products. All parts are available in 16-pin DIP and SO packages. The ADM691A is also available in a space-saving TSSOP package. The following functionality is provided: 1. Power-on reset output during power-up, power-down and brownout conditions. The circuitry remains operational with VCC as low as 1 V. 2. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic. 3. A reset pulse if the optional watchdog timer has not been toggled within a specified time. 4. A 1.25 V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5 V.
ADM691A/ADM693A ADM800L/ADM800M
1VOLTAGE
DETECTOR = 4.4V (ADM693A/ADM800M)
INPUT POWER
7805
+5V
0.1F VCC CMOS RAM
R1
BATTERY
VCC VBATT
BAT ON
VOUT CEOUT ADDRESS DECODE A0-A15 P POWER I/O LINE NMI P RESET
PFI GND R2 NC
ADM691A CEIN ADM693A ADM800L ADM800M WDI
PFO RESET WDO
OSC IN OSC SEL LOW LINE
SYSTEM STATUS INDICATORS
Figure 1. Typical Application
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
ADM691A/ADM693A/ADM800L/M-SPECIFICATIONS
(VCC = 4.75 V to 5.5 V (ADM691A, ADM800L) 4.5 V to 5.5 V (ADM693A, ADM800M) VBATT = +2.8 V, TA = TMIN to TMAX unless otherwise noted)
Parameter BATTERY BACKUP SWITCHING VCC, VBATT Operating Voltage Range VOUT Output Voltage VCC to VOUT Output Resistance VOUT in Battery Backup Mode Min 0 VCC - 0.05 VCC - 0.3 VBATT - 0.3 VBATT - 0.25 VBATT - 0.15 12 20 25 100 1 +0.02 +0.02 VBATT + 0.03 VBATT - 0.03 60 0.1 0.4 0.7 1.5 60 15 100 Typ Max 5.5 VCC - 0.02 VCC - 0.2 0.8 Unit V V V V V V A A A A V V mV V V mA A Test Conditions/Comments IOUT = 25 mA IOUT = 250 mA VCC = 4.5 V VBATT = 4.5 V, IOUT = 20 mA VBATT = 2.8 V, IOUT = 10 mA VBATT = 2.0 V, IOUT = 5 mA VBATT = 4.5 V VBATT = 2.8 V VBATT = 2.0 V VCC > (VBATT - 1 V) VCC < (VBATT - 1.2 V), VBATT = 2.8 V 5.5 V > VCC > VBATT + 0.2 V (VBATT +0.2 V) < VCC , TA = +25C (VBATT +0.2 V) < VCC Power Up Power Down ISINK = 3.2 mA ISINK = 25 mA Sink Current Source Current
1.2
VBATT to VOUT Output Resistance
Supply Current (Excludes IOUT) Supply Current in B. Backup (Excludes IOUT) Battery Standby Current (+ = Discharge, - = Charge) Battery Switchover Threshold VCC-VBATT Battery Switchover Hysteresis BATT ON Output Voltage Low BATT ON Output Short Circuit Current
70 0.04 -0.1 -1.0
1 RESET AND WATCHDOG TIMER Reset Voltage Threshold ADM691A, ADM800L ADM693A, ADM800M ADM800L, VCC Falling ADM800M, VCC Falling Reset Threshold Hysteresis VCC to RESET Delay LOW LINE to RESET Delay Reset Timeout Period Internal Oscillator Reset Timeout Period External Clock Watchdog Timeout Period, Internal Oscillator Watchdog Timeout Period, External Clock Minimum WDI Input Pulse Width RESET Output Voltage 100
4.5 4.25 4.55 4.3
4.65 4.40
4.75 4.50 4.70 4.45
140 1.0 70
15 80 800 200 2048 1.6 100 4096 1024 0.004 0.1
280 2.25 140
0.3 0.4 20 0.4
3.5 RESET Output Short Circuit Current RESET Output Voltage Low LOW LINE Output Voltage LOW LINE Short Circuit Source Current WDO Output Voltage WDO Short Circuit Source Current WDI Input Threshold Logic Low Logic High WDI Input Current POWER FAIL DETECTOR PFI Input Threshold ADM69xA PFI Input Threshold ADM800L/M PFI Input Current PFO Output Voltage PFO Short Circuit Source Current PFI to PFO Delay 0.1 3.5 1 3.5 3 0.75 x VCC -50 10 0.8 -10 20 1.25 1.25 0.01 7 0.4
15
100 0.4
V V V V mV s ns ms Cycles s ms Cycles Cycles ns V V V mA V V V A V V mA V V A A V V nA V A s s
TA = +25C TA = +25C Power Down Power Up Power Up Long Period Short Period Long Period Short Period VIL = 0.4, VIH = 0.75 x VCC ISINK = 50 A, VCC = 1 V, VBATT = 0 V ISINK = 3.2 mA, VCC = 4.25 V ISOURCE = 1.6 mA, VCC = 5 V ISINK = 3.2 mA ISINK = 3.2 mA, VCC = 4.25 V ISOURCE = 1 A, VCC = 5 V ISINK = 3.2 mA, VCC = 4.25 V ISOURCE = 500 A, VCC = 5 V
50 1.3 1.275 25 0.4 100
WDI = 0 V WDI = VOUT VCC = 5 V VCC = 5 V ISINK = 3.2 mA ISOURCE = 1 A VIN = -20 mV VIN = 20 mV
1.2 1.225
3.5 1
15 25 60
-2-
REV. 0
ADM691A/ADM693A/ADM800L/M
Parameter CHIP ENABLE GATING CEIN Leakage Current CEIN to CEOUT Resistance CEIN to CEOUT Propagation Delay CEOUT Short-Circuit Current CEOUT Output Voltage RESET to CEOUT Propagation Delay OSCILLATOR OSC IN Input Current OSC In Input Pullup Current OSC SEL Input Pullup Current OSC IN Frequency Range OSC IN Threshold Voltage OSC IN Frequency with Ext Capacitor
NOTES 1 Either V CC or VBATT can be 0 V if the other > +2.0 V. Specifications subject to change without notice.
Min
Typ 0.005 40 6 0.75
Max 1 150 10 2.0
Units A ns mA V V s A A A kHz V V kHz
Test Conditions/Comments Disable Mode Enable Mode RIN = 50 , CLOAD = 50 pF Disable Mode, CEOUT = 0 V VCC = 5 V, IOUT = -100 A VCC = 0 V, VBATT = 2.8 V, IOUT = 1 A Power Down OSC SEL = 0 V OSC SEL = VOUT or Floating OSC SEL = 0 V OSC SEL = 0 V VIH VIL OSC SEL = 0 V, COSC = 47 pF
0.1 3.5 2.7
12 0.1 10 10 500 VOUT - 0.6 3.65 100 5 100 100
VOUT - 0.4
2.00
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C unless otherwise noted)
ORDERING GUIDE
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . . -0.3 V to VOUT + 0.5 V Input Current VCC (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mA VCC (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA VBATT (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA VBATT (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA GND, BATT ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . 842 mW A Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135C/W Power Dissipation, R-16 Narrow SOIC . . . . . . . . . . . 700 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 110W Power Dissipation, R-16 Wide SOIC . . . . . . . . . . . . . 762 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110C/W Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . 500 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158C/W Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . -40C to +85C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C Storage Temperature Range . . . . . . . . . . . . -65C to +150C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability.
Model ADM691AAN ADM691AARN ADM691AARW ADM691AARU ADM693AAN ADM693AARN ADM693AARW ADM800LAN ADM800LARN ADM800LARW ADM800MAN ADM800MARN ADM800MARW
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Option N-16 R-16N R-16W RU-16 N-16 R-16N R-16W N-16 R-16N R-16W N-16 R-16N R-16W
Table I. Product Selection Table
Part No. ADM691A ADM693A ADM800M ADM800L REV. 0
Power On Reset Time 200 ms or Adj. 200 ms or Adj. 200 ms or Adj. 200 ms or Adj.
Low VCC Threshold 4.65 V 3% 4.4 V 3% 4.4 V 2% 4.65 V 2%
Watchdog Timeout 100 ms, 1.6 s, Adj. 100 ms, 1.6 s, Adj. 100 ms, 1.6 s, Adj. 100 ms, 1.6 s, Adj. -3-
Battery Backup Switching Yes Yes Yes Yes
Base Drive Ext PNP Yes Yes Yes Yes
Chip Enable Signals Yes Yes Yes Yes
ADM691A/ADM693A/ADM800L/M
PIN DESCRIPTIONS
Pin 1 2
Mnemonic VBATT VOUT
Function Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is not used. Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. When VCC is higher than VBATT and is also higher than the reset threshold, VCC is switched to VOUT. When VCC is lower than VBATT and below the reset threshold, VBATT is switched to VOUT. Connect VOUT to VCC if a backup battery is not being used. Power Supply Input; +5 V. 0 V. Ground reference for all signals. Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally switched to VCC. The output may also be used to drive the base (via a resistor) of an external PNP transistor to increase the output current above the 250 mA rating of VOUT. Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold. Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period. (See Table II and Figure 4.) Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 10 A internal pullup. Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than 1.25 V, PFO goes low. Connect PFI to GND or VOUT when not used. Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.25 V. Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply. Output. CEOUT goes low only when CEIN is low and VCC is above the reset threshold. If CEIN is low when reset is asserted, CEOUT will remain low for 15 s or until CEIN goes high, whichever occurs first. Chip Enable Input. The input to the CE gating circuit. Connect to GND or VOUT if not used. Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI is unconnected. Logic Output. RESET goes low if VCC falls below the Reset Threshold. It remains low for 200 ms typ after VCC goes above the reset threshold. Logic Output. RESET is an open-drain output. It is the inverse of RESET.
3 4 5
VCC GND BATT ON
6 7
LOW LINE OSC IN
8
OSC SEL
9 10 11
PFI PFO WDI
12 13 14
CEOUT CEIN WDO
15 16
RESET RESET
PIN CONFIGURATIONS
VBATT VOUT VCC GND BATT ON LOW LINE OSC IN OSC SEL 1 2 3 4 5 6 16 RESET 15 RESET
ADM691A ADM693A ADM800L ADM800M
14 WDO 13 CEIN
12 CEOUT
11 WDI TOP VIEW 7 (Not to Scale) 10 PFO 8 9 PFI
-4-
REV. 0
Typical Performance Curves- ADM691A/ADM693A/ADM800L/M
100 90
1.2
VCC TO VOUT ON RESISTANCE - R
1.1
VCC SUPPLY CURRENT - A
80 70 60 50 40 30 20 -50
1.0
0.9
0.8
0.7
-25
0
25 50 75 TEMPERATURE - C
100
125
0.6 -50
-30
-10
10 30 50 TEMPERATURE - C
70
90
Figure 2. ICC vs. Temperature: Normal Operation
Figure 5. VCC to VOUT ON-Resistance vs. Temperature
60
80 70
BATTERY SUPPLY CURRENT - nA
55
60
50
VCC TO VOUT - mV
ROUT = 0.67 50 40 30 20
45
40
35
10
30 -50
-30
-10
10 30 50 TEMPERATURE - C
70
90
0 40
60
80 IOUT - mA
100
120
Figure 3. IBATT vs. Temperature: Battery Backup Mode
Figure 6. VCC to VOUT Voltage Drop vs. Current
80
70 60
70
ROUT = 7
CEON RESISTANCE -
60
VBATT TO VOUT - mV
50 40
50
30
40
20 10
30
20 -50
0 -25 0 25 50 75 TEMPERATURE - C 100 125 4 6 IOUT - mA 8 10
Figure 4. Chip Enable ON-Resistance vs. Temperature
Figure 7. VBATT to VOUT Voltage Drop vs. Current
REV. 0
-5-
ADM691A/ADM693A/ADM800L/M
10 VBATT = 2.8V 9 8 14 16
PROPAGATION DELAY - ns
12 10 8 6 4 2 0
7
IBATT - A
6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VCC - V 3.5 4.0 4.5 5.0
0
50
100
150
200
250
300
LOAD CAPACITANCE - pF
Figure 8. Battery Current vs. Input Supply Voltage
Figure 11. Chip Enable Propagation Delay vs. Load Capacitance
WATCHDOG AND RESET TIMEOUT PERIOD - s
100
230
220
LONG WATCHDOG TIMEOUT PERIOD RESET DELAY - ms 10
210
200
RESET ACTIVE TIMEOUT PERIOD = > 1 SHORT WATCHDOG TIMEOUT PERIOD
190
180
0.1 10
100 COSC - pF
1k
170 -50
-30
-10
10 30 50 TEMPERATURE - C
70
90
Figure 9. Watchdog and Reset Timeout Period vs. OSC IN Capacitor
Figure 12. Reset Timeout Relay vs. Temperature
7.0
1200
RESET OUTPUT RESISTANCE -
6.5
1000
PROPAGATION DELAY - ns
6.0
800
VCC = 5V, VBATT = 2.8V SOURCING CURRENT
5.5
600
5.0
400 VCC = 0V, VBATT = 2.8V SINKING CURRENT
4.5
200
4.0 -50
-25
0
25 50 75 TEMPERATURE - C
100
125
0 -50
-20
40 70 10 TEMPERATURE - C
100
130
Figure 10. Chip Enable Propagation Delay vs. Temperature
Figure 13. RESET Output Resistance vs. Temperature
-6-
REV. 0
ADM691A/ADM693A/ADM800L/M
100 90
100 90
10 0%
10 0%
1V
400ms
1V
10s
Figure 14. RESET Output Voltage vs. Supply
Figure 15. RESET Response Time
POWER FAIL RESET OUTPUT
RESET is an active low output that provides a reset signal to the Microprocessor whenever VCC is at an invalid level. When VCC falls below the reset threshold, the RESET output is forced low. The reset voltage threshold is 4.65 V (ADM691A/ ADM800L) or 4.4 V (ADM693A/ADM800M). On power-up RESET will remain low for 200 milliseconds after VCC rises above the appropriate reset threshold. This allows time for the power supply and microprocessor to stabilize. On powerdown, the RESET output remains low with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition. If RESET is required to be low for voltages below 1 V, this may be achieved by connecting a pull-down resistor on the RESET line. The resistor will help maintain RESET low down to VCC = 0 V. Note that this is only necessary if VBATT is below 2 V. With battery voltages 2 V RESET will function correctly with VCC from 0 V to +5.5 V. This reset active time is adjustable by using an external oscillator or by connecting an external capacitor to the OSC IN pin. Refer to Table II. The guaranteed minimum and maximum thresholds of the ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaranteed thresholds of the ADM693A/ADM800M are 4.25 V and 4.5 V. The ADM691A/ADM800L is therefore compatible with 5 V supplies with a +10%, -5% tolerance while the ADM693A/ ADM800M is compatible with 5 V 10% supplies. In addition to RESET an active high RESET output is provided. This is the complement of RESET and is useful for processors requiring an active high RESET signal.
Watchdog Timer Reset
The normal (short) timeout period becomes effective following the first transition of WDI after reset has gone inactive. The watchdog timeout period restarts with each transition on the WDI pin. To ensure that the watchdog timer does not time out, either a high-to-low or low-to high transition on the WDI pin must occur at or less than the minimum timeout period. If WDI remains permanently either high or low, reset pulses will be issued after each timeout period (1.6 seconds). The watchdog monitor can be deactivated by floating the Watchdog Input (WDI). If floating, an internal resistor network biases WDI to around 1.6 V.
BATT ON 4.65V1 VCC VOUT VBATT CHIP ENABLE OUTPUT CONTROL CEIN CEOUT
LOW LINE
OSC IN OSC SEL
RESET & WATCHDOG TIMEBASE
RESET & GENERATOR
RESET RESET
WATCHDOG INPUT (WDI) POWER FAIL INPUT (PFI)
WATCHDOG TRANSITION DETECTOR
WATCHDOG TIMER
WATCHDOG OUTPUT (WDO) POWER FAIL OUTPUT (PFO)
1.25V
The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the selected timeout period, a reset pulse is generated. The watchdog timeout period may be configured for either a fixed "short" 100 ms or a "long" 1.6 second timeout period or for an adjustable timeout period. Note that even if the short timeout period is selected, the first time out immediately following a reset is 1.6 sec. This is to allow additional time for the microprocessor to regain control following a reset. The watchdog timer is restarted at the end of reset, whether the reset was caused by lack of activity on WDI or by VCC falling below the reset threshold. REV. 0
ADM691A/ADM693A ADM800L/ADM800M
1VOLTAGE
DETECTOR = 4.4V (ADM693A/ADM800M)
Figure 16. Functional Block Diagram
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output that goes low if the watchdog timer "times out" and remains low until set high by the next transition on the watchdog input. WDO is also set high when VCC goes below the reset threshold. If WDI remains high or low indefinitely, RESET and RESET will generate 200 ms pulses every 1.6 sec.
-7-
ADM691A/ADM693A/ADM800L/M
Changing the Watchdog and Reset Timeout
The watchdog and reset timeout periods may be controlled using OSC SEL and OSC IN. Please refer to Table II. With both these inputs floating (or connected to VOUT) as in Figure 16, the reset timeout is fixed at 200 ms and the watchdog timeout is fixed at 1.6 sec.. If OSC IN is connected to GND as in Figure 16, the reset timeout period remains at 200 ms but a short (100 ms) watchdog timeout period is selected (except immediately following a reset where it reverts to 1.6 sec). By connecting OSC SEL to GND it is possible to select alternative timeout periods by either connecting a capacitor from OSC IN to GND or by overdriving OSC IN with an external clock. With an external capacitor, the watchdog timeout period is Twd (ms) = 600 (C/47 pF) and the reset active period is Treset (ms) = 1200 (C/47 pF) With an external clock connected to OSC IN, the timeout periods become Twd = 1024 (1/fCLK) Treset = 2048 (1/fCLK)
Battery-Switchover Section
When VCC is below the reset threshold, the watchdog function is disabled and WDI goes high impedance as it is disconnected from its internal resistor network. The internal oscillator is enabled when OSC SEL is high or floating. In this mode, OSC IN selects between the 1.6 second and 100 ms watchdog timeout periods.
VCC OSC SEL RESET THRESHOLD 80s RESET
tRS
80s
tRS
RESET
CEIN 12s CEOUT
Figure 17. RESET and Chip Enable Timing
8 OSC SEL
During normal operation with VCC higher than the reset threshold and higher than VBATT, VCC is internally switched to VOUT via an internal PMOS transistor switch. This switch has a typical on-resistance of 0.75 and can supply up to 250 mA at the VOUT terminal. VOUT is normally used to drive a RAM memory bank which may require instantaneous currents of greater than 250 mA. If this is the case then a bypass capacitor should be connected to VOUT. The capacitor will provide the peak current transients to the RAM. A capacitance value of 0.1 F or greater may be used. If the continuous output current requirement at VOUT exceeds 250 mA or if a lower VCC-VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can drive the base of the external transistor. If VCC drops below VBATT and below the reset threshold, battery backup is selected. A 7 MOSFET switch connects the VBATT input to VOUT. This MOSFET has very low input-to-output differential (dropout voltage) at the low current levels required for battery backup of CMOS RAM or other low power CMOS circuitry. The supply current in battery backup is typically 0.04 A. High value capacitors, either standard electrolytic or the faradsize double layer capacitors, can also be used for short-term memory backup. If the battery-switchover section is not used, VBATT should be connected to GND and VOUT should be connected to VCC.
ADM69_A ADM800_
CLOCK 0 TO 250kHz 7 OSC IN
Figure 18a. External Clock Source
NC 8 OSC SEL
ADM69_A ADM800_
NC 7 OSC IN
Figure 18b. Internal Oscillator (1.6 s Watchdog)
8 OSC SEL
ADM69_A ADM800_
7 COSC OSC IN
Figure 18c. External Capacitor
Table II. Reset Pulse Width and Watchdog Timeout Selections
OSC SEL Low Low Floating Floating
OSC IN External Clock Input External Capacitor Low Floating or VOUT
Watchdog Timeout Period Normal Immediately After Reset 1024 clks 600 ms x C/47 pF 100 ms 1.6 s 4096 clks 2.4 s x C/47 pF 1.6 s 1.6 s
Reset Active Period 2048 clks 1200 ms x C/47 pF 200 ms 200 ms
-8-
REV. 0
ADM691A/ADM693A/ADM800L/M
8 OSC SEL
INPUT POWER
ADM69_A ADM800_
7 COSC OSC IN
R1
POWER FAIL INPUT
1.25V
PFO
POWER FAIL OUTPUT
R2
Figure 18d. Internal Oscillator (100 ms Watchdog)
Figure 20. Power Fail Comparator
Table III. Input and Output Status in Battery Backup Mode
WDI
Signal VBATT VOUT
Status Supply Current is <1 A. VOUT is connected to VBATT via an internal PMOS switch. Switchover comparator monitors VCC for active switchover. 0 V. Logic High. The open circuit voltage is equal to VOUT. Logic Low. OSC IN is ignored. OSC SEL is ignored. The Power Fail Comparator remains active in the battery-backup mode for VCC VBATT -1.2 V. With VCC lower than this, PFO is forced low. The Power Fail Comparator remains active in the battery-backup mode for VCC VBATT -1.2 V. With VCC lower than this, PFO is forced low. WDI is ignored. Logic High. The open circuit voltage is equal to VOUT. High Impedance. Logic High. The open circuit voltage is equal to VOUT. Logic Low. High Impedance.
WDO
VCC
t2 t3
RESET
GND BATT ON
t1
t1 t1 = RESET TIME.
t1
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD. t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
LOW LINE OSC IN OSC SEL PFI
Figure 19. Watchdog Timing CE Gating and RAM Write Protection
PFO
All products include memory protection circuitry which ensures the integrity of data in memory by preventing write operations when VCC is at an invalid level. There are two additional pins, CEIN and CEOUT, that control the Chip Enable or Write inputs of CMOS RAM. When VCC is present, CEOUT is a buffered replica of CEIN, with a 5 ns propagation delay. When VCC falls below the reset voltage threshold, an internal gate forces CEOUT high, independent of CEIN. CEOUT typically drives the CE, CS, or Write input of battery backed up CMOS RAM. This ensures the integrity of the data in memory by preventing write operations when VCC is at an invalid level. Similar protection of EEPROMs can be achieved by using the CEOUT to drive the Store or Write inputs of an EEPROM, EAROM, or NOVRAM.
Power Fail Warning Comparator
WDI CEOUT CEIN WDO RESET RESET
An additional comparator is provided for early warning of failure in the microprocessor's power supply. The Power Fail Input (PFI) is compared to an internal +1.25 V reference. The Power Fail Output (PFO) goes low when the voltage at PFI is less than 1.3 V. Typically PFI is driven by an external voltage divider that senses either the unregulated dc input to the system's 5 V regulator or the regulated 5 V output. The voltage divider ratio can be chosen such that the voltage at PFI falls below 1.25 V several milliseconds before the +5 V power supply falls below the reset threshold. PFO is normally used to interrupt the microprocessor so that data can be stored in RAM and the shut- down procedure executed before power is lost.
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APPLICATIONS INFORMATION
INCREASING THE DRIVE CURRENT
INPUT POWER R1 1.25V (PFO) TO P NMI
If the continuous output current requirements at VOUT exceeds 250 mA or if a lower VCC-VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can drive the base of the external transistor via a current limiting transistor.
+5V INPUT POWER PNP TRANSISTOR 0.1F 0.1F
PFI R2 R3
VH = 1.25 1+
R2+R3 R2 x R3
R1
5V
VL = 1.25+R1
1.25 VCC-1.25 R2 R3
PFO
VMID= 1.25
R1+R2 R2
VCC VBATT BATTERY
BATT ON
VOUT
0V 0V VL VIN VM
Figure 21. Increasing the Drive Current
Using a Rechargeable Battery for Backup
Figure 23. Adding Hysteresis to the Power Fail Comparator
Typical Operating Circuit
If a capacitor or a rechargeable battery is used for backup, then the charging resistor should be connected to VOUT since this eliminates the discharge path that would exist during power down if the resistor were connected to VCC.
+5V INPUT POWER I= 0.1F R VCC RECHARGEABLE BATTERY VBATT VOUT 0.1F VOUT - VBATT R
A typical operating circuit is shown in Figure 24. The circuit features power supply monitoring, battery backup switching and watchdog timing. CMOS RAM is powered from VOUT . When 5 V power is present, this is routed to VOUT. If VCC fails, then VBATT is routed to VOUT. VOUT can supply up to 250 mA from VCC, but if more current is required, an external PNP transistor can be added. When VCC is higher than VBATT and the reset threshold, BATT ON goes low, providing base drive for the external transistor. When VCC is lower than VBATT and the reset threshold, an internal 7 . MOSFET connects the backup battery to VOUT.
Reset Output
ADM69_A ADM800_
Figure 22. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the power fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 23. When PFO is low, resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, R3 sources current into the PFI summing junction. This results in differing trip levels for the comparator. Resistors R1 and R2 therefore set the trip point while R3 adds hysteresis. R3 should be larger than 10 k so that it does not cause excessive loading on the PFO output. Additional noise rejection and filtering may be achieved by adding a capacitor from PFI to GND.
The internal voltage detector monitors VCC and generates a RESET output to hold the microprocessor's RESET line low when VCC is below the reset threshold. An internal timer holds RESET low for 200 ms after VCC rises above the threshold. This prevents repeated toggling of RESET even if the 5 V power drops out and recovers with each power line cycle.
Early Power Fail Detector
The input power line is monitored via a resistive potential divider connected to the Power Fail Input (PFI). When the voltage at PFI falls below 1.25 V, the Power Fail Output (PFO) drives the processor's NMI input low. If a Power Fail threshold of 7 V is set with resistors R1 and R2, the microprocessor will have the time when VCC drops below 7 V to save data into RAM. Power supply capacitance will extend the time available. This will allow more time for microprocessor housekeeping tasks to be completed before power is lost.
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ADM691A/ADM693A/ADM800L/M
RAM Write Protection
The CEOUT line drives the Chip Select inputs of the CMOS RAM. CEOUT follows CEIN as long as VCC is above the reset threshold. If VCC falls below the reset threshold, CEOUT goes high, independent of the logic level at CEIN. This prevents the microprocessor from writing erroneous data into RAM during power-up, power-down, brownouts and momentary power interruptions. The LOW LINE output goes low when VCC falls below the reset threshold.
Watchdog Timer
RESET also goes low if the Watchdog Timer is enabled and WDI remains either high or low for longer than the watchdog timeout period. The RESET output has an internal 1.6 mA pullup, and can either connect to an open collector RESET bus or directly drive a CMOS gate without an external pullup resistor.
INPUT POWER +5V 0.1F VCC 3V BATTERY R1 VBATT BATT VOUT ON CEOUT 0.1F
The microprocessor drives the WATCHDOG INPUT (WDI) with an I/O line. When OSC IN and OSC SEL are unconnected, the microprocessor must toggle the WDI pin once every 1.6 seconds to verify proper software execution. If a hardware or software failure occurs such that WDI not toggled a 200 ms RESET pulse will be generated after 1.6 seconds. This typically restarts the microprocessor's power-up routine. A new RESET pulse is issued every 1.6 seconds until WDI is again strobed. The WATCHDOG OUTPUT (WDO) goes low if the watchdog timer is not serviced within its timeout period. Once WDO goes low it remains low until a transition occurs at WDI. The watchdog timer feature can be disabled by leaving WDI unconnected. OSC IN and OSC SEL also allow other watchdog timing options.
CMOS RAM ADDRESS DECODE A0-A15 I/O LINE NMI RESET RESET 0.1F
GND R2 NC
ADM691A ADM693A CEIN ADM800L PFI ADM800M
WDI OSC IN PFO RESET WDO
P
OSC SEL LOW LINE
SYSTEM STATUS INDICATORS
Figure 24. Typical Application Circuit
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ADM691A/ADM693A/ADM800L/M
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP (N-16)
0.840 (21.33) 0.745 (18.93) 0.177 (4.50) 0.169 (4.30)
16 1 9 8 16
16-Lead TSSOP (RU-16)
0.201 (5.10) 0.193 (4.90)
9
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
1
8
PIN 1 0.015 (0.381) 0.008 (0.204) 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
0.280 (7.11) 0.240 (6.10)
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
16-Lead Wide SOIC (R-16W)
0.4133 (10.50) 0.3977 (10.00)
16 9
16-Lead Narrow SOIC (R-16N)
0.3937 (10.00) 0.3859 (9.80)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.1574 (4.00) 0.1497 (5.80)
16 1
9 8
0.2550 (6.20) 0.2284 (5.80)
1
8
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
PIN 1 0.0118 (0.30) 0.0040 (0.10)
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0500 (1.27) BSC
0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
8 0
0.0500 (1.27) 0.0157 (0.40)
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
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PRINTED IN U.S.A.
C2198-12-10/96

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